CSCI E-92: Application Note 5

Number of available interrupt priority levels
---------------------------------------------

The Freescale K70 processor does not implement the full set of 256
possible interrupt priority levels, but instead implements just 16.
Furthermore, the 4 bits used to select the priority level (from 0 to
15) must be in the high-order 4 bits of the 8-bit priority field.
This is true both for the device interrupt priority levels (set
through NVICIPxx) and for the SVC priority level (set through
SCB_SHPRx).

For those of you interested in the supporting information, here are
pointers to the documents:

The ARMv7-M Architecture Reference Manual in section "B1.5.4 Exception
priorities and preemption" on page B1-635 states, "The number of
supported priority values is an IMPLEMENTATION DEFINED power of two in
the range 8 to 256, and the minimum supported priority value is always
0.  All priority value fields are 8-bits, and if an implementation
supports fewer than 256 priority levels then low-order bits of these
fields are RAZ."

And, here is some real information about our own K70.  In the K70
Sub-Family Reference Manual in section "3.2.2.1 Interrupt priority
levels" on page 85, it states, "This device supports 16 priority
levels for interrupts.  Therefore, in the NVIC each source in the IPR
registers contains 4 bits."  The diagram that follows goes on to
confirm that only the high-order 4 bits of each 8 bit field is used.
It doesn't explicitly mention the System Handler (like the SVC
handler) priorities, but they should be handled consistently with the
interrupt priorities.

The K70 Family Product Brief, Rev. 8, 6-2011 in section "4.5.1.2
Nested Vectored Interrupt Controller (NVIC)" on page 17 includes the
following statement, "16 levels of priority, with each interrupt
source dynamically configurable."